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SX1210
ADVANCED COMMUNICATIO NS & SENSING
RL1
LF_M
CL2
CL1
LF_P
Figure 7: Loop Filter
Following the recommendations made in section 3.2.4, the loop filter proposed in the reference design’s bill of
material on section 7.5.3 should be used. The loop filter settings are frequency band independent and are hence
relevant to all implementations of the SX1210.
3.2.7. PLL Lock Detection Indicator
The SX1210 also features a PLL lock detect indicator. This is useful for optimizing power consumption, by adjusting
the synthesizer wake up time (TS_FS), since the PLL startup time is lower than specified under nominal conditions.
The lock status can be read on bit IRQParam_PLL_lock, and must be cleared by writing a “1” to this same register.
In addition, the lock status can be reflected in pin 23 PLL_LOCK, by setting the bit IRQParam_Enable_lock_detect.
3.2.8. Frequency Calculation
As shown in Figure 5 the PLL structure comprises three different dividers, R, P and S, which set the output
frequency through the LO. A second set of dividers is also available to allow rapid switching between a pair of
frequencies: R1/P1/S1 and R2/P2/S2. These six dividers are programmed by six bytes of the register MCParam
from addresses 6 to 11.
3.2.8.1. FSK Mode
The following formula gives the relationship between the local oscillator, and R, P and S values, when using FSK
modulation.
Frf , fsk =
9
8
Flo
Frf , fsk =
9 Fxtal
8 R + 1
[ 75 ( P + 1 ) + S ) ]
3.2.8.2. OOK Mode
Due to the low intermediate frequency (Low-IF) architecture of the SX1210 the frequency should be configured so
as to ensure the correct low-IF receiver baseband center frequency, IF2.
Frf , ook =
9
8
Flo ? IF 2
Frf , ook =
9 Fxtal
8 R + 1
[ 75 ( P + 1 ) + S ) ] ? IF 2
Note that from Section 3.3.4, it is recommended that IF2 be set to 100 kHz.
Rev 2– Sept 8 , 2008
th
Page 16 of 73
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